Towards grid parity: advances in c-Si PV manufacturing technology

Lower cost c-Si panels support a key goal for solar known as grid parity, where it costs the same to generate power on rooftops as it does to buy it from the grid

K. Macwilliams, J. Shu, A. Moretto, F. Ahmad, 
Applied Materials, Santa Clara, CA USA

Lower cost c-Si panels support a key goal for solar known as grid parity, where it costs the same to generate power on rooftops as it does to buy it from the grid.

Recent climate policies announced by China and the United States state a common goal of a 17% emissions reduction, which is equal to slightly more than a 40% reduction in emissions intensity by 2020. Energy from renewable sources, including solar photovoltaics (PV) energy, is expected to play a key role in reaching this target.

The current market for solar PV is dominated by crystalline silicon (c-Si) solar panels, and c-Si solar technology is expected to continue to dominate in the residential and commercial rooftop markets due to higher efficiency and rapidly reducing costs. There has been a 40% price reduction since the middle of last year, largely as a result of the improved supply of polysilicon, which is the basis of c-Si-based panels. When supply was constrained by limited production of polysilicon, the price reached over $300/kg. Now, the cost has fallen to below $100/kg and supplies are readily available for mass production — driving a continuing decline in panel prices.

Lower cost c-Si panels support a key goal for solar known as grid parity, where it costs the same to generate power on their rooftops as it does to buy it from the grid. This point has already been reached during the peak demand period (Fig. 1). According to the European Photovoltaic Technology Platform group, solar PV is expected to reach grid parity in most of Europe over the next 10 years [1] (Prof. Wim Sinke 2009).

Fab of the future: improving productivity

The solar industry has shown a 7% year over year cost reduction [2], most of which stems from improvements in manufacturing. As the industry strives to reach grid parity at all times, not just at peak demand, it is essential to continue improving manufacturing efficiencies. To achieve this goal and build the solar fabs of the future, innovations in automation and factory throughput must be implemented (Fig. 2).

Automation. Future factories will grow larger to gain economies of scale and to support the increasing demand for solar cells. These factories are expected to be from 500MW to 1GW in capacity, compared with today’s norm of 50-200MW. Also, in order to fabricate higher efficiency cells, manufacturers will move to more complex process flows that require 10-15 process steps, compared to 7 today. The result is that the number of wafer movements will increase by a factor of ten. This dramatic increase will require expanded factory automation. Furthermore, improvements in wafer handling will be required as wafer thicknesses decrease from ~180μm today to 120-140μm.

High productivity cell processing. The cost of each processing step must be reduced in order to drive down the cost of solar. This requires high productivity systems optimized for individual processes to gain the highest overall processing speed with minimum maintenance. The industry’s target for the next generations of tools is to double throughput within the same footprint.

Yield improvement and metrology. There is a wide distribution of individual cell efficiency in today’s factories. Lower efficiency cells and wafer breakages cause yield losses of up to 5%. By using metrology to keep manufacturing processes tightly controlled, it is possible to tighten the distribution of cells close to the best performers. Further, sorting of incoming wafers can eliminate those with microcracks and other defects that are likely to cause lower yield and disruptions in-line due to wafer breakages. Implementing metrology along with automatic process control (APC) and statistical process control (SPC) can further reduce process drift, helping to reduce the end costs while increasing the average cell efficiency.

Factory control systems. In today’s factories there are very few industry standards and few factories use a manufacturing executive system (MES). Even in cases where there is an MES system in the factory, the equipment is written with custom software to communicate with the MES system. This reduces the functionality of MES systems and capabilities like recipe controls, wafer/lot tracking are not common. The solution is to use communication standards throughout the industry and use powerful factory control systems to allow for fluent communication between the equipment and the factory control systems. Such standard systems will allow the factory to cope with the challenge of increasing wafer moves while also improving errors due to mismanagement of process recipes that result in mis-processing of wafers.

Cell technology improvements drive down cost/W

Recent efforts have brought cost/W to about $2/watt for crystalline silicon solar panel technology, with some companies forecasting $1/watt around 2013-14. There are several ways to lower the cost/W by raising cell efficiency (Fig. 3).

Techniques to increase cell efficiency include:

  • Selective emitters: Differing phosphorus doping levels are created in the emitter and contact areas. Light doping of the emitter regions minimizes recombination losses while heavy doping at the surface of the silicon beneath the metal lines minimizes contact resistance.
  • Double-printed contacts: Narrow, tall metal lines are printed in two passes to minimize shading losses.
  • All back contact structure: Moving all contact lines to the back surface reduces the shading losses to virtually zero.
  • Anti-reflective coatings: a SiN passivation arc layer can reduce surface reflection from 30% to <10%.

Screen print technology advancement

Metallization is performed on both sides of the wafer to conduct electrons out of the cell. This is most commonly done with screen printing, where a conductive paste is forced through the openings of a fabric screen onto the wafer. Screen printed wires are designed to achieve a very low electrical resistance to allow the current to flow freely. However, the metal wires occupy more area on the front of the wafer, and since they are made with silver, which is not transparent to light, part of the cell is shadowed by the metal from the sun, thus reducing the amount of electricity produced. The solution is to create very thin but very tall wires to preserve the current-carrying capacity while reducing the shadows cast on the cell surface. Unfortunately, this is not easy to do with standard screen printing equipment.

Double-printing technology

Applied Materials’ Baccini group has developed a method that allows printing two or more layers of silver paste one on top of each other (Fig. 4). The Esatto technology allows printing a second layer of material on top of a first layer of material with high accuracy and reliability, achieving ±15μm alignment repeatability at 1,500 wafers per hour, 24/7. To achieve such precision, this technology combines state-of-the-art screen printing equipment, high precision mechanical parts, dedicated vision systems and proprietary software algorithms. Other important factors are optimized conductive paste and screen characteristics. This technology also enables cell manufacturers to increase cell efficiency from 16% (typical for a mainstream multi-crystalline solar cell) to 16.5%( experimental results may vary from 0.3%-0.5% range of cell efficiency increase).

Screen print selective emitter technology

The double-printing technology described above can also be used to implement other emerging solutions such as selective emitters. The standard process, homogenous emitters combined with firing-through process, is widely used in the photovoltaic industry. This technology produces a fixed phosphorus concentration on the entire front surface of the wafer that is a compromise between achieving good metallic contact resistance and acceptable bad passivation of the front side active regions.

The selective emitter concept offers substantial benefits over the standard process in that it allows for creating two emitter doping levels: highly doped regions beneath the front contact fingers to reduce contact resistance and lightly doped active regions between contacts to improve the passivation effect to decrease recombination and thus increase current and open-circuit voltage.

Selective emitters can be formed at the wafer by either screen printing a resist mask, by screen printing an etchant on an oxide barrier layer or by screen printing a doping ink before metallization.

Screen printed all back contact patterning

Screen printing is extendable to a number of different applications. For example, the highest efficiency commercially available c-Si solar cells have a structure that places all contacts on the back surface of the wafer, reducing the shadowing effect to virtually zero. Baccini screen printing technology can be used instead of expensive photolithography to achieve the complete patterning process at much reduced cost.

Advanced passivation technology

Surface passivation is an important thin film application for solar cell processing. A large positive fixed charge density is very important for achieving low surface recombination velocities for p-type crystalline silicon surfaces. Antireflective layers on the wafer surface have multiple functions:

  • Maximizing light absorption and, at the same time,
  • Creating the condition for good electrical passivation of the silicon surface
  • Protecting grain boundary defects in silicon

High quality SiN anitrefloective films can be achieved with multi-layer stacks to co-optimize antireflection and passivation properties. High effective lifetime and high cell efficiency can thus be demonstrated with this type of film stack. SiN Passivation film quality becomes even more critical with lightly doped emitter like selective emitter device to achieve low surface recombination velocities. For advanced technology cell technology, multi-layer passivation films will become a standard.

Multi-film stacks can also be made for n-type or back contact passivation with the requirement of eliminating positive fixed charge. The interface can be an oxide to improve surface passivation without positive charge with a SiN film on top for bulk passivation. Optimized surface and bulk passivation can be easily achieved by altering the film stack composition.

Advanced cell architecture technology

There are several companies that already break the 20% cell efficiency barrier. Sanyo’s Hit cell recently announced 23% efficiency at the research level and is moving to mass production. SunPower’s all back contact cell design and novel manufacturing processes has reached cell efficiency of 21% in mass production. Suntech’s Pluto line boasts 17.2% efficiency in multi-crystalline cell and close to 20% in mono-crystalline cell performance.

We are anticipating more companies will join the over 20% high efficiency club. At PVSEC 2009, Fraunhofer published results with n-type cell with front side boron emitter achieved 23% cell efficiency. Suniva also announced its above 20% cell efficiency roadmap with selective emitter, advanced metallization in the front and point contact in the back all using screen print techniques.

Advances in wafering

Advances in wafering technology can reduce each of the main costs of wafering: polysilicon material, wire, slurry and equipment. The primary strategy is to minimize costs by cutting thinner wafers at high yields while reducing the silicon lost during processing.

Diamond wire is a new technology that has the potential to reduce slurry, wire and equipment costs by replacing the conventional combination of plain wire and abrasive slurry with a diamond-bearing wire and lower-cost abrasive-free cutting fluid. The technology consumes much less wire, using a few km per silicon load instead of few hundred km for conventional processing. However, current prices for diamond wire are very high, which has limited practical application to ingot shaping applications. Diamond wire may also increase the productivity of the equipment, allowing a manufacturer to reduce equipment costs by reducing the number of machines needed for a given factory output.

Significant improvements in conventional wire saw productivity are also reducing costs. The Applied HCT MaxEdge wire saw can cut up to 13MW of wafers in a year using a unique dual wire management technology and is designed to cut using wire as thin as 120μm.

Despite recent price reductions, polysilicon is still the highest single cost in wafering: 40% of the silicon is lost as waste particles as the wire cuts through the ingots. There are some promising technologies that aim to recover the polysilicon from the slurries at low cost. Thinner cutting wire can also reduce the polysilicon loss.

Also, wafering technologies are adapting to help reduce costs in other part of value chain. Both mono and multi-crystalline ingots are increasing in size to reduce the ingot growing costs. These ingots must be sawn into smaller sizes for wafering. The new generation of squaring and cropping tools needs to support cutting these larger ingot sizes.


The drive to reduce carbon emissions will create high demand for green technologies. To open the electricity market for solar PV, low cost, scalable manufacturing will be necessary. Fully automated manufacturing solutions with yield management and control systems will be required. Advanced technologies such as thinner wafers, selective emitters and, advanced passivation and advanced cell architecture will also reduce the cost/W.


MaxEdge is a trademark of Applied Materials.


Ken Macwilliams received his PhD in electrical engineering from Stanford U. and is VP of Technology and New Products, Applied Materials, Crystalline Silicon Solar Business, 3050 Bowers Avenue, Santa Clara, CA 95052 USA; email 

Jen Shu received her PhD in chemical engineering from Cornell U. and is the director of customer integration at Applied Materials, Crystalline Silicon Solar Business Group

Andrea Moretto received his masters degree in mechanical engineering from Padua U. and is the Global Product Manager for the Baccini Cell System at Applied Materials.

Farhan Ahmad received his bachelor’s of technology degree from IIT Kanpur and is the Global Product Manager for the Crystalline Silicon Solar Business Group at Applied Materials.


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