In terms of the real estate it occupies, the silver conductor grid that is typically screen printed onto the front face of silicon solar cells has gone through something of a revolution in recent years. This ongoing process is being driven by – and is in its turn driving – a number of new and emerging technologies, that, working together, are enabling the solar industry to achieve ever increasing efficiencies as it moves along the road towards grid parity. In this article, we look at a few of the developments that are enabling cell manufacturers to produce finer conductor grids, and at some of the technologies, in particular selective emitter (SE), that are emerging as a result.
The move towards finer conductors is being driven by some very powerful issues, perhaps the most important of which is the fact that they block sunlight from reaching the light energy-converting strata within the silicon wafer. Thus the narrower they are the better. Another compelling driver concerns their distribution over the cell: for the converted energy to be harvested successfully as usable energy, the electrons freed in the light energy conversion process must be allowed to migrate easily and with minimum resistance into the conductor grid, which means that the more surface area it covers, the better.
At first glance, it seems that these two issues call for diametrically opposed solutions – one for minimal, the other for maximal coverage of the silicon wafer by the grid. In fact, the solar industry is succeeding in accommodating both needs within a single elegant solution: conductor miniaturization. Significant reductions in the width of the individual conductors allows them to be printed closer to one another in well-distributed grids, allowing more sunlight into the wafer to ensure maximum energy conversion while at the same time providing sufficient coverage to optimize the cell’s energy harvest.
So it is that industry standard conductor widths, at around 150µm just four years ago and 120µm a couple of years ago, are between 80 and 100µm today (in an industry that, two years ago, was convinced that sub-100µm conductors were unachievable). Even now, the trend continues apace – for solar’s highest-tech flagship products, 60µm conductors are being printed in commercial production environments, while 40µm capabilities are firmly on the radar for some cell-making pioneers (Fig. 1).
|FIGURE 1. High-aspect ratio 42µm-wide stencil printed frontside conductor.|
In support of miniaturization
Of course, cell manufacturers are not alone in their endeavors – alongside them are many industry partners working to develop the materials, tools, equipment and techniques that have made these changes possible.
For example, one of the keys to this degree of fine-line printing is the print screen itself. At our company, for example, we are able to draw on a wealth of expertise in stencil and screen design and printing processes. One of our ongoing projects, is the development of a hybrid printing screen that combines the best of both conventional screen and electro-formed stencil technologies to enable the creation of very high-aspect ratio conductors. We are also studying a special two-stage high aspect-ratio metallization process developed by the Netherlands-based Energy Research Centre, ECN, that uses stencils for the production of extremely narrow conductors. (Fig. 2)
|FIGURE 2. Developments in stencil technology enable very high-aspect ratio conductors. This image shows a 30µm-wide aperture in a nickel stencil.|
A great deal of work is also going into the production of finer wires for screen manufacture. Standard solar industry print screens are currently built using 20-25µm wires, while top-end commercial production may use finer 18µm products. This looks poised to drop still further to a tiny 11µm thanks to special alloys now under development – an achievement that will yield the finest screens yet, with over 800 wires per inch. Although these development screens use exotic materials that are currently over an order of magnitude more expensive than standard screen meshes, we expect to see costs drop as they enter more commercial production – just as they did for the 18µm products now in common use.
In parallel with these advances and in order to get the most from them, ultra-fine photo-imageable screen printing emulsions incorporating new chemistries and finer particulates are being designed to improve resolution capabilities to well below the current 40µm limit (Fig. 3)
Paste vendors, too, have done a remarkable job in enabling cell manufacturers to print the narrower, higher aspect ratio conductors that are fast entering the industry’s mainstream. As features continue to shrink however, they face the added challenge of increased conductor contact resistance. This is because standard silver paste tends to sit on top of the silicon wafer, with just a few scattered crystals penetrating slightly into, and connecting with, the wafer. This means a less efficient transfer of electrons from the wafer to the conductors – a problem that increases as conductors come down in size. Recognizing this, paste vendors have already developed a number of products designed specially to optimize electrical contact, and work is ongoing for the future.
|FIGURE 3. Screen manufacture advances will allow for resolution capabilities far below the 40µm limit. This image shows a 30µm-wide aperture in an ultra-fine wire mesh screen.|
Progress in all of these areas has enabled the development and introduction of numerous technologies and techniques that, in their turn, have further driven cell efficiencies in general, and miniaturization in particular. These include print-on-print, a technique now used in commercial production that optimizes the height (and therefore the current-carrying capacity) of very narrow conductors by printing the grid pattern twice over using special screens, emulsions and high-aspect ratio printing pastes. Another process under development that benefits from, and may well drive the need for miniaturization, is the “seed and plate” (S&P) technique. Here, a 30-40µm silver seed line is printed onto the wafer, then over-plated using silver in an electrolytic process. In the Fraunhofer Institute’s light-induced plating process, this second pass uses light to activate the cell, which in turn powers the plating stage. The advantage of S&P is that the superior conductivity of the plated silver combines with the connectivity of the seed line to offer much improved cell performance. The downside is that it adds a further and somewhat complex manufacturing process to the solar cell manufacturing line.
Another approach to solar cell manufacture that is dependent upon miniaturization, and at the same time, promises to drive it still further, is selective emitter (SE), by which the phosphorus that forms the cell’s energy-converting p/n junction, and which facilitates electron migration, is present in varying concentrations across the cell. Although SE has been the subject of numerous articles in the trade press, it is worth taking a moment here to look at why it is such an important development for the industry.
The heart of any silicon-based solar cell is its p/n junction. This is normally formed in the early stages of cell manufacture by firing the wafer in a phosphorus-rich atmosphere, thereby diffusing a uniform, planar layer of phosphorus a few hundred nanometers into the upper zone of the wafer. Here, photons of sunlight release electrons that migrate through the silicon to the cell’s front face where they are captured by the conductor grid, where they flow to the aluminum contact on the cell’s reverse side to rejoin their electron-poor, “holey” atoms. In so doing, they create the cell’s electrical current.
It is clear that maximum efficiency relies on everything working optimally – on the photons generating sufficient electron/hole pairs, and on these migrating to the right places and being collected properly. And this is where the issue lies. The very material that is instrumental in giving the p/n junction its functionality also forms a significant barrier to light: the top part of the cell where the phosphorus is most concentrated, can in fact “waste” up to a massive 30% of incident light in the blue part of the spectrum, with the electrons recombining within the wafer before they get to the grid, producing heat rather than useful current.
SE mitigates these losses by limiting the higher concentrations of phosphorus to the areas directly under the silver collection grid. Here, the phosphorus can do no harm as this area of the cell is in shadow, and at the same time it improves the contact between the silicon and the grid, facilitating electron migration. The area between the grid, on the other hand, contains relatively low levels of phosphorus, optimizing the cell’s blue response and increasing efficiencies.
While this is good news for a cell’s energy conversion capabilities, it is less good for its energy harvesting capabilities, as the lower phosphorus concentrations result in higher sheet resistance, hampering electron migration. The solution for such SE cells is to place the conductors even closer together than in conventional cells, which again brings us back to the need for very fine grid features – which is one of the reasons SE, while it has been around for close to 30 years, is only now coming into its own.
Manufacturing selective emitters
Over the years, numerous methods have been proposed for the manufacture of SE cells, but the candidates for broad use are most likely to be those based on laser technologies. One such approach takes advantage of the phospho-silicate glass layer that forms on the surface of the wafer during the standard diffusion process. This would normally be removed after the diffusion process, but in Manz’s one-step laser doping process, this is first laser written, driving more phosphorous into the silicon where the silver grid will subsequently be printed. More complex and costly, but extremely effective in producing high efficiency cells for the top end of the market is the buried contact process, whereby deep trenches are laser- or saw-cut through several passivation, doping and emitter layers. These trenches are further doped and then metallized, creating extremely narrow, extremely high aspect-ratio conductors that reduce the shadowing effect immensely. A simpler approach that adds just a single, simple manufacturing step to the conventional cell manufacturing cycle is Innovalight’s Cougar process. Here, the conductor grid is printed onto a previously printed silicon grid that acts as a localized doping agent, facilitating electron migration into the conductors and boosting efficiencies significantly.
Which technology or technologies ends up being applied in mainstream cell manufacture will depend on a number of criteria. One of these, and possibly the most critical for cell efficiencies, is the precision with which the dopant is printed. At present, the doped areas, being invisible, tend to be much wider than the conductors themselves, which means that we are failing to capture potentially convertable energy. Just as precision printing processes allow us to create finer conductors, that same precision together with repeatable accuracy and state-of-the-art alignment techniques will enable us to increase cell sensitivity and energy conversion and harvesting capacities by matching those conductors with the invisible ultra-fine doped areas.
In this way SE will not only be driven by ultra-fine printing capabilities, it will also drive further developments in miniaturization. This situation shows that solar cell manufacture is never about isolated developments. Rather, it is a delicate and complex balance of technologies, materials, techniques, parameters and issues that are so inextricably linked that changes in one area will invariably have broader ramifications elsewhere. Just as progressive miniaturization is enabling print-on-print, S&P, SE, and a host of other technologies to move into commercial production, it is in turn being driven by them and other factors in the quest for higher efficiency, lower cost photovoltaic cell production.
Tom Falcon is senior process development engineer at DEK Solar, 11 Albany Road, Granby Industrial Estate, Weymouth DT4 9TH United Kingdom; ph.: +44 1305 208415; email email@example.com.