Recent developments raise the possibility of achieving optimization of key parameters such as thin wafers, low-kerf, and high yield.
Andy Skumanich, SolarVision Consulting, Los Gatos, CA USA
The wire saw cutting of silicon ingots is a key step in the production of photovoltaic (PV) cells based on crystalline silicon—it has been in place for multiple decades and has been a reliable approach to providing the wafers used for cell manufacturing. Recently announced improvements from the major wire saw suppliers allow for the technology to carry forward into the next few generations. With the overall drive for lower production costs in PV production, which in turn is leading to thinner wafers, these new systems will provide the necessary capabilities for the near term. However, the wire saw approach will begin to show some constraints due to its inherent limitations for the subsequent ultra-thin generations where the wafers enter the sub-100µm regime.
The wire saw process, by its nature, removes almost 50% of the starting poly, which is not easily recovered. In partial compensation, to use—and to lose—less poly, the PV wafers are getting thinner, dropping from the current 200µm down to 150µm in 2010, and subsequently, even thinner. This reduction in thickness poses significant challenges for wire saw wafering. A review of current wire saw capabilities will highlight the current capabilities and the upcoming demands. Although significant advances are being implemented that will extend wire saw capabilities, there are radically new approaches that are being aggressively developed, which present completely new methods for generating wafers. The alternatives present opportunities, but still remain to be production proven. This article gives a basic understanding of the wafering process, some of the challenges, and some of the newly developing directions in wafering.
Reducing the cost of wafers
The major segment of the solar PV industry is based on crystalline silicon (c-Si) wafers, which holds 90% of the market. The key metric for PV is the cost per watt ($/W) and any opportunity to lower the production costs is actively pursued. The wafer forms the literal basis for the PV cell, and contributes a significant percent of the overall cost. As a result, there is extensive effort addressing wafer manufacturing, and the ability to reduce the costs.
Over the last few years, the high cost of poly led to high costs in wafers, and resulted in a major focus on this segment of the production chain. Inherent in the cutting process is kerf-loss, which is the silicon that is cut and lost as particles in the slurry. The main considerations include the following points: the ability to 1) cut thinner wafers, 2) minimize the kerf-loss, 3) achieve a good yield, and 4) attain high throughput, all the while maintaining 5) the lowest possible processing cost (i.e., low $/W). There is a complex trade-off between these five conditions. However, it is necessary to optimize all five points, and especially point 5—lowering costs.
The wire saw cutting process
The wafer cutting process consists of starting with a brick of silicon, either multi-, or mono-crystalline Si. Typical dimensions of this brick are 0.25m long by 125 × 125mm or 156 × 156mm. This brick is then glued and mounted onto a holder and placed into the wire saw where there is a spool of wire with a suspension of grit particles of SiC in a slurry. The wire is guided onto the brick by a threading unit that spaces the wires at intervals along the brick. The wire spacing and the wire diameter determine the wafer thickness and the kerf-loss. The length of wire is on the order of hundreds of kilometers, and runs at a speed of ~20m/sec. A cut takes about 5 to 8 hours. The slurry is continuously fed and acts as both the cutting material and the coolant. At the end, the wire cuts through the brick and the process stops. Then the wafer set is demounted, the wafers are separated—singulated—cleaned, and then collected.
One of the most important considerations is the reduction in wafer thickness. There has been significant market pressure to reduce both the thickness and the kerf-loss as a means to address the high cost of starting poly material and achieve better cost savings. Figure 1 shows the timeline of the projected dimensions for thickness. (Note that the kerf-loss is about equal to the wafer thickness until 120µm.) Unlike the semiconductor industry, there is no single roadmap, but rather a general consensus. Currently most wafers are in the 200µm range with 200µm kerf-loss. The indications are that by 2010, the industry leaders will be introducing cells based on wafers around 150µm, although SunPower is already at this thickness for their current generation high efficiency cells. The thickness reductions from 2003 to 2013 would represent a gain of almost 3x in poly utilization.
Figure 1. Wafer thickness roadmap. Source: Dr. Richard Swanson 2008, NREL 2008, and SVC 2009.
Of course, this reduction in wafer dimension has its challenges, not the least of which is cost control. Cuts as thin as 80µm wafers have been achieved in the lab under carefully controlled conditions. Ironically, the cutting may turn out easier than the post-cut processing and handling—the big issue is breakage. Generally, as the wafers get thinner, the various flaws that remain or that are induced by cutting, cause wafers to break. The challenge is to not just to cut the wafers, but to then be able to demount, singulate, clean and handle them. Finally, there are significant processing challenges for converting the wafers into optimally functioning cells (see “Ultra-thin wafers pose significant processing challenges”).
Current capabilities in the wafering sector
There are two dominant companies in the wire saw wafering segment, Meyer Burger and Applied Materials (the former HCT company). Both have recently released the latest equipment lines targeting the above five key points. Typically, to produce thinner wafers, traditional wire saws had to reduce the ingot length (load) and the cutting speed, but the new systems address those limitations to an extent. Meyer Burger has the D271, which allows for wafers to be cut to 120µm with comparable kerf and a baseline throughput of 500wph. The Applied Materials line now includes the MaxEdge, which has comparable overall numbers.
Although the high level features of the two tools are similar, the approach of the companies to address the yield and the throughput has some distinct differences. One of the major issues for thin wafers is that the guide cut wire must also become thinner. During the cut, the wire may wear to the point of breakage, which is the worst possible fault because if this occurs well into the cutting process, the whole block is likely lost. Meyer Burger has active and extensive metrology in its system that provides a real-time break detection where the system can immediately stop, and there is the potential to recover and resume. Applied has an alternative approach to divide up the drives into two separate wire spools and reduce the wear seen by a single wire. Both approaches allow the wafers to be reliably cut to the 150 and 120µm dimensions for thickness. However, these solutions do flag the concern about using ever-thinner wires and increasing cutting speeds for wafering. The cutting of a wafer is an intricate balance between the wire properties, the cutting medium, and impact on the wafer (such as sub-surface damage, and with-in-wafer thickness control—TTV—see “Ultra-thin wafers pose significant processing challenges” for importance).
The complexity of cutting a wafer
It may seem that cutting a brick of silicon is not much of a subject, but this impression is surprisingly wrong. First, there is significant research going into the science of the process itself. Second, there is an extensive application engineering element to develop a production-ready recipe matrix. Third, all of the applications must conform to lowering $/W. With regards to the first, there is now a new center of research being inaugurated by Fraunhofer under the guidance of Dr. H. Moeller, a leading wire-saw scientist. This center in the “Solar Valley” of Germany will focus exclusively on advancing wire saw technology.
The above brief description does not do justice to the relatively complex recipe matrix needed for the actual cutting process. The cut depends on the pitch, the cutting speed, the wire dimensions, the brick dimensions, the type and size of grit, the slurry and coolant used, and the various levels of change tolerated during the cutting process. No one cut wafer set is necessarily the same as another set—there is a real art to cutting wafers. These complexities promise to increase dramatically as wafers start to be cut at the 100µm level. At this point, the wire saw begins to impact a more significant proportion of the wafer thickness because the sub-surface damage penetration depth stays constant even while the thickness drops. In addition, the kerf loss becomes greater than the wafer thickness itself. For below 100µm wafers, even though the wire saw can produce 80µm wafers, there is significant concern that the five key conditions will not be achievable. Although the need for sub-100µm wafer is still likely to be more than five years out, there are already attempts underway to provide the needed capabilities that may obviate the wire saw limitations.
Future developments and kerf-free wafering
Some recent developments raise the possibility of achieving the optimization of the five key conditions from above for the ultra-thin wafers: including of course, thin wafers at or below 100µm, low-kerf, and lower cost. On the near-term horizon is the use of fixed-abrasive diamond coated wires. Diamond wire reduces kerf-loss and aids silicon recovery, and both the silicon dust and the wire can be reused. Because no grit is used, the kerf is at the same size of the wire and so can be reduced. The latest advancements are making the cost of these wires achieve the necessary $/W reduction, and within a few years it is likely that the fixed-abrasive wires will become part of the set of five key conditions. This approach is likely to bring the wire saw to near the 100µm limit even though there may be some issues of surface conditions that need to be resolved. For going to below the 100µm level, alternatives to wire saw are being developed.
On the more innovative side for the alternatives, there may be an opportunity to reduce the kerf-loss to zero. One company, Silicon Genesis (SiGen), has recently announced the capability to generate kerf-free wafers by using an elegant implant/cleave process, which leads to a wafer exfoliation that does not require singulation, nor cleaning. According to recent statements, SiGen can produce wafers at thicknesses ranging from 150µm down to 20µm with no kerf-loss. SiGen has indicated that it is transitioning from R&D into pilot capability for the 150–120µm regime and its 20µm solution is also under active development. Note that at a thickness of only 20µm, the wafers really become more like foils, and in fact start to border on the a-Si/ µc-Si thin film sector at 2µm deposited by PECVD onto glass. The difference of course is the foils are freestanding and are true c-Si materials with the potential for high efficiency.
Another approach for the ultra-thin foils, being developed by Silicon Valley start-ups, is one based on epitaxial growth of silicon. In this latter case, a substrate is used to provide a basis for gas-phase to solid-phase epi-deposition. The starting material is silane gas, which then grows into a 20µm or thicker c-Si foil, which is subsequently removed. The crux of this epi c-Si approach is to address the throughput and the cost considerations that make up the top five key requirements. Typical epi conditions are relatively slow, meaning low throughput, and require moderately expensive reactors. The most captivating aspect of the 20µm foils now coming out of these companies is that the foils are truly flexible and resemble plastic sheets. There is even the possibility of reduced breakage because the silicon foil is more flexible and consequently more compliant and handling tolerant. If these new capabilities do indeed provide the approach to achieve the five key parameters, and in addition provide more easily handled wafers/foils, then the PV industry will be able to carry on with the dramatic cost reductions needed for the market for the further-out cell generations.
Handling of wafers
No discussion of thin wafering would be complete without expanding on the handling aspects of very thin, and ultra-thin wafers. The module manufacturers want lower cost wafers, so if thinner means less cost, then that’s better. However, if thinner means more breakage, there is yield loss, hence higher costs. Further, if the breakage happens in the field from the thin wafers from stresses during the processing or handling, that’s even worse. So there is a good amount of study and engineering being devoted to handling thin and very thin wafers. As one example, there are researchers at the Texas Manufacturing Assistance Center (TMAC) who were part of an SAI – BP Solar project. They had developed a prototype air system able to both acquire wafers from a stack and move them along a track with no moving components. A similar approach based on Bernoulli grippers will acquire wafers but must use manipulators and robotic elements to move wafers through the production line. An example of the TMAC capability is shown in Fig. 2.
|Figure 2. TMAC air-levitation scheme. Source: Dr. Raul Fernandez at TMAC.|
For some of the current approaches, they now cause pop-out holes in the ultra-thin wafers where they make contact. So, it will be necessary to have innovative approaches such as the TMAC system in 5–8 years for handling the sub-100µm wafers. On a more mundane level, the notion of wafer processing may also have to return from the batch mode to the belt mode, or some modification of a belt-like platen to hold the wafers. The belt mode has recently been replaced at various cell lines for batch because of the abilities of batch processing to provide good uniformity and high throughput at cost-effective levels. However, for sub-100µm wafers and certainly for 20µm foils, the use of cassettes will not be viable in their current state.
There is significant activity in the wafer generation segment of the PV industry reflecting the focus on the two key ingredients for solar PV: technology improvement and cost reduction. The wafering segment may seem to be low tech, but the processes needed for creating the next-generation of thin wafers below 150µm, and the subsequent ultra-thin wafers below 100µm, the challenges are anything but low tech.
Equally important is that any technical solution must absolutely provide lower overall costs for the final PV product—the module. In that regard, thinner wafers will use less poly, but they must be resistant to breakage and allow for processing to capture the necessary light to provide high conversion efficiencies of 20%. The fascinating extrapolation of the current progression of PV wafers is to 20µm foils of c-Si that are 156mm squares and are no longer rigid wafers. These foils pose a dramatic challenge to achieving 20% efficiencies, but they open up a range of potential applications such as building integrated PV (BIPV), where the building’s outer skin generates electricity. Meanwhile, the leading wire sawing companies are making rapid progress to help the industry achieve the more near-term goal of lower PV costs for wider adoption.
Andy Skumanich received his PhD in physics at the U. of C. Berkeley and is founder and principal consultant at SolarVision Consulting, Los Gatos, CA; firstname.lastname@example.org.
Ultra-thin wafers pose significant processing challenges
Current best-method processes can accommodate wafers to ~150µm, but below that are a multitude of issues beyond breakage that present challenges. However, many companies as well as research institutes are focusing significant efforts to develop capabilities to generate high efficiency thin wafer cells.
To digress from the wafering step and give a flavor of the processing issues, there is the range from the practical to the fundamental. On the practical side, PV wafers have a back surface contact made from Al paste, and the thin wafers are susceptible to bowing, which is a major problem for the module manufacturers. On the scientific side, the thinner wafers have less light absorption, consequently, various sites are working on methods to increase the effective light path, and the light trapping.
As Fig. S1 shows, the cell efficiency tends to drop off below 100µm. In this figure, the modeled cell efficiency shows a decrease to 100µm with a drop off below 80µm depending on various cell features. The goal is to find ways to push the drop-off to the lowest points with tricks such as high reflectance back surfaces that can effectively double the wafer’s apparent thickness to incoming light. With the right top surface treatment, the light can be trapped to further increase the cell efficiency.
Figure S-1. Cell efficiency dependence on wafer thickness (modeled). Source: Dr. Ajeet Rohatgi, Georgia Institute of Technology.
The wafer-to-cell process is not so subtly affected by the wafer cutting parameters. The very first step in the cell formation is the texturization step, which is critical to achieving good light trapping. If the wafer cutting is changed, even if the given specified wafer parameters remain the same, it is possible for a variation in the cutting process to alter the wafer enough so that the texturization step falls outside the window. The resulting top surface becomes sub-optimal, and the cell has reduced efficiency. To repeat, wafering is indeed an art, especially because it must be paired with the downstream processing.
One last point: the culmination of the research and the recipes must merge so that the overall $/wafer cost is driven lower and lower. A higher cutting speed may give better throughput, but there may be greater wafer “total thickness variations” (TTV). For wafer processing, the control on some of the key steps requires sensitive temperature tuning; in particular this is true for the thermal treatment to sinter the contacts and back surface. For this step, if there are greater TTV excursions, some parts of the wafers will be outside the process window and the overall cell efficiency will suffer. The TTV is a key wafer specification. So even if during the cutting process more wafers are produced per unit time (lower overall cost per wafer), if the wafer features make cell production harder and their yield is lower (higher overall cost), then the net result is — no benefit. As these last two simple examples illustrate, there is an interwoven complexity in the wafering process parameters, the cell processing, the cost, and the net result (Fig. S2)
|Figure S-2. Predictable cost reductions. Source: Dr. Richard Swanson – SunPower, and SVC.|
–From the May/June 09 issue of Photovoltaics World magazine–