New Hampshire, United States [Solid State Technology magazine] Photovoltaic cells are getting steadily more efficient, and even the small area taken up by interconnect is shrinking to get more electrons flowing. Some of these developments were discussed at a recent Photovoltaic Specialists Conference in Philadelphia and at the accompanying PV America exhibition.
An average efficiency of 19.1% for p-type crystalline silicon (c-Si) is achieved in SunTech’s new Pluto cells, according to David Greene, U. of South Wales, Australia, who claimed Pluto 2 coming later this year should boost this to 20%-21%.
One key to improved efficiency, he explained, is the use of 10μm interconnect lines vs. 100μm in present commercial cells—achieved without the use of costly optical lithography. Details were not presented, but Greene said screen printing—the basic process for commercial PV cells—is employed.
Even incremental improvements in efficiency are of great interest for solar panels, according to Andy London, global business manager for Heraeus’ photovoltaic business unit in West Conshohocken, PA. Solar panels operate for 25 years or more, so even efficiency improvements of 0.2% or 0.3% will get an enthusiastic response from users, he said.
Currently, typical efficiencies for commercial c-Si cells are 16% (poly-Si) to 17% (mono-Si), according to London, with 19%-20% in the labs.
Almost all silver paste used for interconnect on present commercial cells comes from DuPont, with a uniform formulation. But London explained that substrates from each vendor differ because of variations, such as in phosphorous doping or nitride coatings. Heraeus’ alternative approach customizes each silver paste for individual wafers, optimizing additives to improve performance, such as lower resistivity and better adhesion, which can add to conversion efficiency.
The silver paste is screen-printed onto the surface of a wafer (front and back) and heated to 800-850°C for 2sec to melt through the SiNx coating and make ohmic contact to the phosphorous-doped silicon below. Traces are typically 100μm wide, with 80μm coming soon and 50μm in R&D, according to London.
(This article appears in the October issue of Solid State Technology)