PVWorld caught up with a handful of executives presenting at the recent Intersolar conference in Munich, Germany …
PVWorld caught up with a handful of executives presenting at the recent Intersolar conference in Munich, Germany (May 27–29) who provided summaries of their talks, which ranged from PV “roadmap” suggestions to technologies for kerf-free foil and dicing using lasers and thermal stress.
Last July, Silicon Genesis announced its entry into the solar PV market with a kerf-free wafering process called PolyMax. That announcement was followed four months later by news of the company’s new facility starting production of 150µm kerf-free PV wafers. In March of this year (3/4/09), the company announced it had produced a 20µm mono-crystalline Si kerf-free, 125mm2 PV foil.
Figure 1. Accelerating grid parity. [Source: Barclays Capital (Solar Energy Handbook), Silicon Genesis calculations]
At last week’s SMET Advanced PV Technology conference, company president/CEO, Francois Henley, presented performance data for the new material (Figure 1). He also made a case for the company’s PolyMax technology (at 150µm) already besting (at $0.18/W) the equivalent price of $0.24/W—the target for polysilicon modules to be competitive with grid electricity, according to a Barclays Capital source (Solar Energy Handbook) (Figure 2). [Editors’ note: In Fig. 2, cell efficiency is the amount of silicon needed to generate 1W of energy and is expressed in grams/W. So in 2008, if it takes 9g/W of polysilicon at $80/kg to make a module, multiply to get a cost of $0.72/W.]
The graph in Fig. 2 shows that in order to reach grid parity in 2012, the polysilicon cost has to be equivalent to $0.24/W. The only way to reach this target is to have both the poly price come down as well as the wafers become thinner and thinner (using less material). “Even with overall polysilicon prices dropping, we have shown that kerf-free is essential to make solar energy not just an alternative source, but a standard renewable energy source,” Henley told PVWorld.
Although the company has made even its thinnest version of PolyMax (20µm) available to cell manufacturers, what will be required is the ability of manufacturers to be able to handle such thin wafers.
Today’s PV technology landscape is still dominated by crystalline silicon (c-Si), roughly 85% market share vs. 15% for thin-film technologies. Both areas will continue to enjoy relative market growth, but thin-film technologies and new concepts will close the gap, predicted Winfried Hoffmann, CTO of Applied Materials’ solar business group.
For c-Si, cost decrease is coming from thinner wafers (from 450µm down to 180µm) and better efficiency (improving from 12%–14% to 17%–22%); sub-100µm thickness and stable 19%–24% efficiency are realistically achievable within the next decade, he said.
The one route for thin-film technologies to achieve lowest cost and price per m2 is in building-integrated photovoltaics (BIPV), where homogeneous appearance and semitransparency take primary importance over conversion efficiency, Hoffmann said.
He also noted the parallels in PV manufacturing to LCDs, with a push to use bigger substrates—from 0.6m2 to up to 5.7m2 for Applied’s SunFab lines, and eventually pushing toward 10m2—and use of similar large-area amorphous silicon deposition processes and tools. Likewise, “there is a parallel development for low cost and price per Watt, like a-Si/µc-Si and II-VI compound semiconductor materials,” he said, where emphasis is on efficiency; look for today’s 8%-11% module efficiency to improve to 12%-14% in the coming years, “with potential for further increase.”
Terry Behrens, senior director of manufacturing integration at CH2M Hill, presented a “roadmap” approach to adapt in-line manufacturing optimization techniques that are applied to the specific needs of a solar manufacturing facility at SMET 2009. The method includes tailoring approaches to different wafer, cell, and thin-film module processing requirements.
Behrens told PVWorld that the methodology also can be applied to multiple locations, enabling comparison of factory sites. “These models enable owners to first forecast and then improve their plants’ capital improvement, investment strategies, plant expansions, time-to-market ramp up time, optimal production output, and competitive position as benchmarked against peer operations,” he said.
Data presented included three case studies. The first was a 300MWp a-Si line, for which the analysis was able to redefine transportation paths and space to eliminate material handling bottlenecks and relocate buffer positions and size to best support continuous facility operation. The changes increased production output by 15%, reduced material handling capital investment by 10%, and saved 5% on space, said Behrens.
Figure 2. Tracking future growth of the global PV solar market; electricity market in GWp and €B turnover. (Source: Applied Materials)
In a second case study, a 200MWp facility, the optimization process was able to achieve an integrated production and waste management solution, a new automation basis supporting productivity for bottleneck tools, and updated overall AMHS transaction requirements to significantly reduce the risk of material handling bottleneck conditions. Behrens said that the efforts resulted in a 10% capital cost reduction in the waste management equipment set.
In a third case study (300MWp a-Si facility), the integration of the site layout with the production layout analysis resulted in major changes. The end result was a 10% increase in output, a 15% reduction in the projected process piping costs, and an 18% reduction in production space.
Hans-Ulrich Zühlke, Jenoptik’s business development manager, presented data on the company’s thermal laser separation (TLS) dicing method, which separates brittle materials by thermal induced mechanical stress (see “Thermal laser separation for wafer dicing,” Solid State Technology, May 2009, p. 26). As a result of the thermal treatment method, mechanical stress is generated within the wafer material, which, at a well-defined point is strong enough to open and guide a crack, Zühlke told PVWorld. “This process is self-centering and independent from the lattice plan and orientation of the material,” he said. The cleaving process requires no protective coating or cleaning after dicing is required.
Results of the TLS process are extremely smooth edges, with almost no chipping and a negligible heat affected zone, Zühlke noted. “Based on the cleaving principle, the kerf width is zero and the yield can be increased by reducing the street width,” he said. This cleaving technique works for standard-Si-based wafers as well as for GaAs and Ge, he noted, though there are some differences. “Compared with silicon, the heat conduction of GaAs and Ge is significantly lower and these materials are more brittle,” he said. Therefore, much thicker wafers can be separated with the same laser power. The figure shows a blank Ge wafer (150µm thickness) that was separated into dies of 2mm x 2mm.
Jenoptik used its prototype system to separate 675µm thick wafers reporting that, for vertically integrated semiconductor devices, there was an increased blocking voltage, which Zühlke noted should be an additional motivation to use TLS for CPV devices. —D.V., J.M.
NanoGram stays focused on multi-crystalline silicon for PV apps
Silicon has many advantages for solar application: it’s a well-known material with well-characterized performance data, field-proven for solar applications with high conversion efficiency and a demonstrated 30-year lifetime. Speaking at a recent SEMI PV Group luncheon, NanoGram president/CEO Kieran Drain outlined his company’s SilFoil 35µm multi-crystalline silicon technology (mc-Si) as its chosen path to achieve grid parity.
NanoGram’s LRD technology.
SilFoil deposits a thin sheet of silicon that, on a morphology basis, is actually the same as slicing a cast ingot. The company has achieved a 64% reduction in silicon on prototypes at the mini-module level (150mm2), he said.
Drain described three levels of differentiation in the company’s proprietary technology that are keys to achieving high efficiency at a low cost: laser reactive deposition (LRD), high-temperature silicon deposition, and zone melt recrystallization (ZMR). The LRD process uses an optically modified CO2 laser beam whereby silane gas is split into silicon metal and hydrogen. The laser deposition process is used to create a release layer with a melt temperature well above that of silicon, followed by a silicon deposition on that release layer. The ZMR process is used to do very precise wide-format, high-cooling-rate melt re-crystallization.
A 5MW line (pre-production devices) is slated for completion in 4Q09 in Milpitas, CA. — D.V.