IMEC research energetically stacks up

Advanced Packaging’s Gail Flower reports from presentations at IMEC’s recent annual research review, centering on two areas of predicted high growth: crystalline Si and organic solar cells, and 3D stacked ICs including through-silicon vias (TSV).

IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages and photovoltaics, two areas of predicted high-growth, IMEC has announced notable achievements.

Click to Enlarge
Jef Poortmans, program director of photovoltaics and professor at Katholieke Universiteit Leuven, reviewed what IMEC has to offer in crystalline Si and organic solar cells. Crystalline Si will remain the material of choice for solar cells for the next decade, but to support market growth at the present rate, the cost of cells will have to go down and efficiencies must improve. These are IMEC’s goals, along with developing the next generation of wafer-based bulk silicon solar cells and epitaxial cells.

Today the photovoltaic market is growing at an annual rate of 40%, and of that market, crystalline Si solar cells have a 90% share. The amount of silicon used will have to be reduced by a factor of 2 while efficiencies improve by 25%, going from 16% to 20% for industrial crystalline Si solar cells. Other components, such as metallization layers, surface and contact passivation, should be produced more efficiently as well and with cheaper materials.

Jef Poortmans, Ph.D., department director solar and organic technologies, IMEC.

“Since we started working on solar cells in 1984, R&D on crystalline Si solar cells has formed the backbone of our activities,” says Poortmans. At present, IMEC is working with wafer-based bulk silicon solar and epitaxial cells. The roadmap aims to reduce active silicon layer thickness from 150μm down to 40μm by 2020. Efficiencies should reach 20% if meeting future goals. Click to Enlarge

Looking at the big picture, IMEC plans to follow several macro trends, he said: “Reduce the grams of Si/W, reduce the wafer loss and thickness, increase efficiency by 20%; reduce manufacturing costs by equipment scaling, fab scaling, reduce expensive materials, standardize, integrate cell manufacturing; speed up the learning curve with new technologies, accelerated the reduction of feed-in-tariffs, and develop PV-dedicated equipment.”

Besides research using generic bulk silicon for solar cells, epitaxial thin-film silicon solar cells on low-cost silicon carriers will also be developed. Epitaxial thin-film silicon solar cell technology is expected to be the intermediate step before mainstream fabs switch from bulk to thin film-like solar cells. Whereas the process is similar, the epi-process can be implemented with limited equipment investment. To improve the optical confinement of light in the active part of the cell, a buried porous Si reflector will be integrated in this future thin-film solar model.

Large area i-PERC solar cell on a thin wafer.

In organic solar cells, IMEC’s associated laboratory, IMOMEC on the campus of Hasselt U., developed a method to stabilize the morphology of organic solar cells. With these stabilized solar cells, efficiencies were achieving that compare with state-of-the-art solar at 4% efficiency. Under long-term operation, all solar cells based on a mixture of organic semiconductors deteriorate due to the segregation of the mixture of compounds, thus reducing the conversion of light into electricity. However, in the latest method, IMEC has fixed the nanomorphology of the polymers and prolonged operational lifetime of the cell.

Click to Enlarge
Transmission electron microscopy for polymer/PCBM 1:1 active layers after degradation at 100°C for 2hrs, showing phase segregation for the Rieke P3HT polymer (left), but a stable morphology for the novel polymer organic solar cell.

3D ICs, TSVs

In October IMEC engineers demonstrated the first functional 3D integrated circuits made by die-to-die stacking using 5μm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13μm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25μm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.

Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results were presented at the IEEE-IEDM conference in San Francisco in December 2008.

Click to Enlarge
3D stacked IC with die-to-die stacking using copper through silicon vias (TSVs).

With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, program director of IMEC’s Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies, including equipment and materials suppliers Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Others include SATS provider Amkor; foundry SMC; ICOS Vision Systems for EDA work; fabless company Qualcomm; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.

Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after the FEOL, but before the actual BEOL. It takes advantage of the high-aspect-ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.

Click to Enlarge

“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.

IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration — fab, packaging, or board-level assembly. The different 3D interconnect types include 3D-SIP, which uses traditional packaging interconnect technologies with wire-bonded stacked die, stacked packages or 3D interconnects at the 2nd and 3rd Jisso packaging identified levels. Another flavor is called 3D-WLP for 3D interconnects made post IC passivation or those at the 1st Jisso level. Finally, 3D-IC and 3D-SIC could happen
at the IC foundry level, Jisso’s level 0. These would be 3D-SIC with 3D interconnects at the global or intermediate level of the chip wiring hierarchy. Or they could be 3D-IC which interconnects at the immediate chip level.

Eric Beyne, Ph.D., scientific director advanced packaging and interconnect center (APIC).

Finding the 3D technology design sweet spot with the best of power, cost, performance, and content remains a challenge. With IMEC’s recent advancements, the technology has matured and the next step is to

provide a clear roadmap for bringing these packages to the marketplace. IMEC engineers are using PathFinding, a virtual design flow process to help optimize and evaluate critical points for TSV alignment, electro migration, yield, and test process steps.

This article originally appeared in Solid State Technology.

Previous articleThrough Thick and Thin: Efficiency not supremacy is the aim for duelling technologies
Next articleIndustry Veterans Form Solar Group

No posts to display