Dr. Fred Seymour, PrimeStar Solar, a wholly owned subsidiary of GE, describes how the company is defining its factory design optimization parameters as it ramps CdTe manufacturing. Dr. Daniel Josell, NIST, discusses how 3D architecture is used to achieve lateral carrier separation, and back-contact technologies are beneficial. Debra Vogler caught up with them at MRS Spring 2011.
Debra Vogler, senior technical editor
May 3, 2011 — Dr. Fred Seymour, PrimeStar Solar, a wholly owned subsidiary of GE, describes how the company is defining its factory design optimization parameters as it ramps CdTe manufacturing. Dr. Daniel Josell, NIST, discusses how 3D architecture is used to achieve lateral carrier separation, and back-contact technologies are beneficial as they reduce carrier diffusion length.
CdTe in the lab
Dr. Daniel Josell, a metallurgist at NIST, presented paper #C2.4 (“Fabrication and performance of dual back-contact thin film photovoltaic [CdS/CdTe] devices”) at the MRS Spring Meeting (4/27-29, 2011, San Francisco, CA). He noted that 3D architecture is used to achieve lateral carrier separation and back-contact technologies (taller electrodes) are beneficial as they reduce carrier diffusion length. Enabling measurement of 3D effects was the primary goal of the work.
“The big issues for PV are contact-related,” said Josell. He added that superfill is a natural choice for creating 3D contacts, which potentially could have intricate geometries and/or more contact area. The NIST researchers demonstrated the processes for fabricating the devices, the impact of annealing and microstructural issues, and they also showed that these processes are feasible for cadmium sulfide (CdS)/cadmium telluride (CdTe) thin film photovoltaics. Though Josell commented that the CdS/CdTe materials system is not necessarily the best choice.
Electrodeposition — while not necessarily required for all the layers — is required for the first layer to differentiate the electrodes, explained Josell. The devices only achieved a 1% efficiency because of reactions with the underlying substrate due to the CdCl2 anneal that is required in order to get CdTe to perform. However, “for material systems that wouldn’t require a halide anneal, one might anticipate avoiding such reactions with the substrate,” said Josell.
NIST recently brought on-line a pulsed-laser deposition system, so the researchers will be working on other material systems and deposition capabilities. One such project is the systematic variation of the electrode geometry and/or metallization.
CdTe in the manufacturing plant
Speaking at the MRS Spring Meeting, Dr. Fred Seymour, VP of technology at PrimeStar Solar, a wholly owned subsidiary of GE, describes how the company is defining its factory design optimization parameters as it ramps its newest 400MW manufacturing facility, which was announced on April 7. On the same date, GE reported the company had achieved an efficiency of nearly 13% on a full-size CdTe thin-film solar panel.
In a podcast interview after presenting paper #C1.6 (“Scaling CdTe PV from pilot production to high-volume manufacturing”), at the MRS Spring Meeting, Seymour says that the company has been taking a systematic approach, throughout the GE organization, to accelerate the down selection of the appropriate methods and techniques that are the most likely to result in more efficient cadmium telluride (CdTe) solar cells.
|Podcast interview about ramping CdTe for PrimeStar Solar: Play Now or Download
Upon studying the materials system (CdTe), there are plenty of indications that the efficiency entitlement is present, noted Seymour. It is therefore expected that the record of 16.5-17% efficiency set in 2001 can be broken. “It’s up to us to go out and find it,” said Seymour.
The company is also optimizing its factory design considerations based on operating costs (bill-of-materials [BOM], labor costs, overhead, etc.), module efficiency, and capital cost.
More from MRS Spring Meeting 2011:
- Lighting the paths for LED materials
- The III-V future of CMOS, the return of spin-on low-k
- Thin film PV in Symposium C
- Memory, hardmasks, low-k — nothing’s confidential
- Outside CMOS fabrication, but respecting boundaries