The recent shortage in the solar wafer market is expected to revert to a potential oversupply in the next quarters. The competition will be intensified with limited differentiation in cost and quality, which could lead to significant price drops starting in 1H ’11 .
The commoditized and oversupplied wafer market represents a daunting challenge to new entrants, even without including the recent multiple GW capacity increases announced by major Asian suppliers. The companies with low cost manufacturing and higher material quality will prevail in this market.
Figure 1. PolyMax properties/performance: a) (left) Wafer-to-wafer as-cleaved average thickness (solid line) and within-wafer thickness max and min (broken lines); b) (right) AFM surface roughness of as-cleaved wafers of various thicknesses.
There has been great interest in identifying and developing kerf-free wafering approaches [2,3]. Industrializing kerf-free wafering technology has, however, proven challenging. Most technologies have only been demonstrated at the small lab-scale without surmounting practical or technical issues to move to high-volume manufacturing operations .
Figure 2. a) (left) QSSPC effective lifetime measurements on (111) 100µm PolyMax wafers; b) (right) 20µm PolyMax wafer undergoing a custom 2-point bend test.
A high-volume, low cost method of manufacturing kerf-free crystalline silicon wafers has been developed – called PolyMax [5,6]. The process, based on ion beam-induced cleaving of crystalline silicon bricks, has been demonstrated to produce consistently high quality c-Si wafers ranging from 20µm to 150µm in thickness. The advanced material properties such as total thickness variation (TTV), surface roughness, minority carrier lifetime and mechanical strength are presented and discussed in this article.
The process consists of two primary steps that proceed in a cyclic manner until the silicon brick is fully converted to wafers. One wafer cycle consists of first implanting the brick surface with a hydrogen ion beam to develop a sub-surface cleave plane followed by a cleaving step to slice a 125mm x 125mm or 156mm x 156mm wafer. The ion beam energy determines the cleaved wafer thickness while the brick cropping step determines its surface dimensions (e.g., pseudo-square, square shape).
Figure 3. Materials roadmap – SEMI PV Group. Source: PV Technology Roadmap Forum – Materials
During the first step, a high energy hydrogen (proton) beam irradiates the top surface of silicon bricks or ingots. The incident mono-energetic protons lose their energy as they traverse into the silicon material and come to rest at a pre-determined depth to form a stressed cleave layer. The silicon wafer thickness is thus accurately determined by the depth or range of the implanted protons, which in turn is controlled by the energy of the proton beam. Implant energies of 1-4MeV are required to fabricate silicon wafers of 20µm-150µm in thickness suitable for solar photovoltaic use. For example, a 2MeV implant will produce a 50µm wafer, while a 3MeV implant will yield 85µm wafers. During a single implant run, a total of 36, 156mm x 156mm bricks (6×6 array) or 64, 125mm x 125mm single crystal silicon bricks (8×8 array) are batch processed for high-volume manufacturing.
During the second step, the implanted silicon brick is induced to fracture, or cleave, in a highly controlled manner along the implanted ion stress layer. A single wafer of silicon is detached from each brick and the process is subsequently repeated on the newly exposed brick surface. Repeating implant and cleave cycles will thus convert a silicon brick to its equivalent thickness of wafers. As opposed to using wire-saws, the cleaving technique essentially eliminates expensive silicon material waste due to kerf loss.
The elimination of sawing kerf loss combined with its ability to make thinner wafers of high quality make the implant-cleave wafering approach technically and economically attractive. For example, while a typical silicon usage to make a solar wafer including kerf loss is approaching 6g/W, the new implant-cleave process consumes merely 2.5g/W at its highest thickness of 150µm. Using $50/kg for the price of polysilicon, this corresponds to a 60% cost savings in silicon material. Higher savings occur when the new method’s unique ability to make thinner wafers is utilized.
The new wafering method cleaves rather than saws, and this fundamentally affects the amount of variation in wafer thickness and roughness during the manufacturing process. Not only are the variations much smaller than wafers that have been wire sawed, the implant and cleave physics cause a linear coupling between these variations and the wafer thickness. For example, a 150µm PolyMax as-cleaved wafer will typically have a variation of +/- 2µm and RMS roughness of 0.4µm, but a 20µm PolyMax wafer will show thickness variation of less than +/- 0.2µm and RMS roughness of 0.06µm. This strong thickness-variation interdependence is what enables the method’s ultra-thin thickness roadmap
Thickness measurements have been made on several wafers of 85µm as-cleaved thickness target. Figure 1 (left side) shows average wafer thickness (solid line) and the within-wafer maximum and minimum thickness (broken lines). They were performed on 9 sites within each 156mm x 156mm pseudo-square wafer using a Heidenhain MT101M gauge. Wafer-to-wafer thickness variations are roughly ± 1µm. Total thickness variations (TTV) across each wafer are approximately of the same magnitude or better. In contrast, any wire-sawn wafers have total thickness variations of at least an order of magnitude larger.
Surface roughness of the as-cleaved wafers as measured with an AFM (atomic force microscope) is typically less than 1μm RMS (20µmx20µm scan area). Figure 1 (right side) shows the roughness-thickness dependence of the process that enables ultra-thin wafer cleaving.
Wafer carrier lifetime considerations
The RF quasi-steady state photoconductance (QSSPC) method using a Sinton WCT-120 was used to characterize the excess minority-carrier lifetime of the wafers . Prior to the measurements, all “as-cleaved” wafers underwent lifetime recovery steps that include annealing, etching, cleaning and surface passivation. The annealing and etch steps were used to remove implantation damage. When used in PV cell manufacturing, the surface damage etch step and thermal diffusion step would be substitutive. Remaining processes include cleaning and wet passivation. Effective lifetimes on 100µm layers are over 200µs at minority carrier density MCD 1·1015cm-3 (Fig. 2, left side). Assuming a surface recombination velocity of about 10-20cm/s range as typical for passivation of chemically prepared Cz-Si (111) surfaces, the measurement corresponds to a bulk lifetime of over 600µs. This is close to the P-type bulk lifetime of the brick material.
For a quantitative assessment of a silicon wafer’s mechanical strength, it is often useful to take measurements of the wafer’s surface stress to fracture [8,9]. The challenge was to develop practical test methodologies for wafers that are generally too thin for conventional surface strength test methods. For surface stress to fracture tests, a miniaturized ring-on-ring test setup scaled to the lower wafer thickness was adopted. The test serves to isolate a 4mm diameter area of wafer for testing so that an average fracture force can be measured over the wafer surface. Using this method, the wafers have consistently shown to be of equal or greater mechanical strength than conventional wire sawn wafers, even after the saw-mark damage surface removal etch (Table 1).
Table 1. Comparison of fracture forces for wet chemical etched wafers.
Even at lower thicknesses where wire sawn wafers are unavailable for comparison, the ultra-thin wafers exhibit impressive mechanical qualities. In the case of the ultra-thin 20µm thick wafers (called a silicon “foil” due to its high flexibility), the high strength of the wafers can be demonstrated in a custom-designed, two-point bend test where a full wafer is shown to be capable of bending with a radius of curvature as small as 5mm, even before any surface treatment has been added. Building-integrated PV (BIPV) and other applications requiring flexible absorbers can now be of high conversion efficiency.
The “PV Technology Roadmap Forum” held by SEMI’s PV Group  discussed the roadmap for solar wafers materials using the traditional wire saw according to Fig. 3. The wafers produced using SiGen’s technology exceeds even the 2020 PV Technology roadmap specifications in terms of wafer thickness, TTV, roughness and mechanical strength.
The material properties of the wafers produced by the new implant-cleave approach discussed above were presented and compared to traditional wire-sawn wafers. With its ability to enable wafer manufacturing of 20µm to 150µm thickness without kerf loss, the new method is positioned to emerge as a low cost high quality wafering approach supporting the fast growing crystalline silicon PV market.
PolyMax is a trademark of Silicon Genesis Corporation.
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 R. Brendel, “Review of Layer Transfer Processes,” Wiley-VCH, Weinheim, ISBN: 9783527403769, 2003.
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 A. Fujisaka, “Keeping Pace with Cost Reduction as Module Prices Continue to Decline,” Photovoltaics World, pp 38-41, July/August 2010.
 R.A. Sinton, A. Cuevas, M. Stuckings, “Quasi-Steady-State Photoconductance, A New Method for Solar Cell Material and Device Characterization,” Proc of the 25th IEEE Photovoltaic Specialists Conference, pp. 457-460, 1996.
 ASTM International Standard C1499-05, 2005, “Standard Test Method for Monotonic Equibiaxial Flexural Strength of Advanced Ceramics at Ambient Temperature,” ASTM International, West Conshohoken, PA.
 G. Coletti, N.J.C.M van der Borg, S. De Iuliis, C.J.J. Tool, L.J. Geerligs, “Mechanical Strength of Silicon Wafers Depending on Wafer Thickness and Surface Treatment,” Proc. of the 21st European Photovoltaic Solar Energy Conf. Dresden, Germany, 2006.
 SEMI PV Group, “PV Technology Roadmap Forum,” Germany, June 2010
Alessandro Fujisaka received his BS in electrical engineering from the U. of Sao Paulo and is head of sales and marketing at Silicon Genesis, 145 Baytech Drive, San Jose, CA 95134 USA; ph.: 1-408-228-5858; email [email protected].