Three key elements in a photovoltaic (PV) device define the basis of its manufacturing technology: 1) the semiconductor, which absorbs light and converts it into an exciton; 2) the semiconductor junction, which separates the photo-generated carriers; and 3) the contacts on the front and back of the cell. The two main categories of technology are shaped by the choice of the semiconductor: 1) crystalline silicon in a wafer (90% market share) or thin film (3% market share); and 2) thin fi lms of other materials (7% market share).
Plasma texturing has proved particularly suitable for advanced solar cell structures
and new low-cost substrates
Silicon substrate processing for solar cell fabrication, which was mainly inherited from the IC-industry, has been further developed to address a greater variety of substrates and device formation specifi cs. Two types of crystalline silicon are used as substrates: monocrystalline (c-Si), produced by slicing wafers from a highpurity single crystal CZ or FZ boule; and multicrystalline (mc-Si), made by sawinag a cast or columnar block of silicon or growing a ribbon of Si, either as a plain two-dimensional strip, or as an octagonal/dodecagonal column (EFG), by pulling it from a silicon melt and laser wafering.
In order to achieve grid parity ($$/pW), PV technology strives to increase the power conversion efficiency (PCE) while reducing cost-of-ownership (CoO). The former is done by minimizing both optical and electrical losses – and implies advanced surface texturing and cleaning. The latter entails low cost material and technology utilization, which leads one to conclude that the industry will place its bet on polysilicon.
Solar cell performance
The performance of a solar cell is a critical function of its internal quantum effi ciency (IQE), which determines the relative percentage of photogenerated EHPs lost to recombination after accounting for refl ection losses. Being a material with an indirect band gap, silicon’s absorption coefficient is relatively low, and therefore light management in the solar cell has to be optimized. Hence, the primary goal is enhancement of light absorption in the wavelength range corresponding to an AM1.5 irradiation spectrum for terrestrial applications (AM1.0 – for space products), while minimizing recombination losses and leakage through the parasitic junctions.
The light-trapping scheme takes advantage of the fact that due to the high refractive index n of silicon, the light inside a silicon specimen that propagates outside a narrow angular cone defined by the critical angle (Θc=Sin-1(l/n) is subjected to total internal reflection. Therefore, by re-directing light inside Si at oblique angles (>Θc), total internal reflection causes multiple bounces within the cell, thus enhancing its absorption probability. Detailed statistical analysis has shown that in comparison with a planar sheet, the effective absorption can be enhanced by as much as a factor of 4n2 [1].
To reach this statistical limit, however, surface texture must fully randomize incident light. Therefore optimal texture dimensions needed to achieve this statistical randomization are comparable to light wavelengths inside Si. The enhanced absorption in sub-wavelength structures is based on the waveguide resonances in λ/2n type cavities [2]. Efficient surface texturing can reduce the reflectance from >35% to <10% and improve absorption in the infrared (IR) region without compromising minority carriers lifetime.

Monocrystalline substrates
If the substrate is monocrystalline, it is advantageous to make use of the anisotropic etching properties of Si in an alkaline solution. As the {111} planes get etched more slowly than other crystal planes, {111} facets are developed. On <100>wafers, this leads to pyramidal shapes at the surface that are particularly effective in reducing reflectance. A regular array of pyramidal pits with facets at 54.7º to the horizontal plane — called inverted pyramids — can be formed using oxide etch mask with reflectances as low as 8% without ARC. However, in industrial practice, masked processes are avoided [3]. From a manufacturability point of view, it is appealing to combine the saw damage removal and alkaline texturing in one single step, in which case a trade-off has to be made between process speed and quality of the surface treatment.
After alkaline etch, a neutralization step in a dilute HCl solution and extensive DI water rinse are required. The widely used mixture of diluted NaOH, or KOH with IPA as a wetting agent, is always optimized for the specific substrate morphology, types of impurities, and defect distribution.
Alkaline concentration can vary from 2–3% to 20–30%, reaction temperature from 20ºC to 120ºC, and time from 2–3 min to 60–80 min. Follow up steps can include RCA2, CP (chemical polishing), and standard cleaning [4]. In some cases, IPA is replaced with a more sophisticated surfactant (aromatic compounds with aliphatic group) that shortens the time of the combined texturing-cleaning procedure and provides, as an additional benefit, a substantial increase in a wafer’s mechanical stability (low breakage rate) that is vital for reduced thickness technology [5].
Multicrystalline substrates
Alkaline random texturing is not effective on multicrystalline silicon substrates due to its anisotropic nature. Some grains (typically those with an orientation close to <111> normal to the surface) remain untextured, leading to a high average reflectance. A very elegant technique of texturing mc-Si is to etch the wafers in an acid mixture based on HF and HNO3.
The HNO3 tends to oxidize the surface, while the HF etches the oxide away. The etching process occurs preferentially at defects. Therefore, when saw damage is present, this etching process structures the surface in a way that is independent of the crystal orientation [6]. This acidic isotexturing results in lower reflection than traditional anisotropic etching on multicrystalline material, and better conversion efficiency (Fig. 1).
After acidic texturing, wafers are usually dipped in a dilute alkaline solution to remove a thin porous silicon layer that is formed during the texturing step (stain etch). This is followed by a neutralization step to remove all Na or K atoms from the surface before emitter diffusion.
Due to the large variety of mc-Si types of substrates featured by different structural defect density, their strain field and decoration pattern of critical impurities (C, B, P, Me) acid texturing recipe is often altered by adding diluents such as DI H2O; H3PO4; H2SO4; NaNO2 to improve selectivity and catalyze the reactions [7].
Most sophisticated texturing recipes that aim to increase the minority carriers’ lifetime would even use incremental change in bath concentration and/or reaction time to compensate for a specific part of ingot from which the substrate was cut in order to address critical differences in grain quality and oxygen concentration (Fig. 2) [8].
Isotropic wet texturing requires the presence of surface defects to work effectively. On substrates without saw damage, such as Si ribbons or EFG sheets, acidic texturing either does not work, or presents issues of process uniformity and reproducibility [9]. Both alkaline and acidic etch produce double-sided topography on a substrate. While these technologies are the most commonly used by far and have a very well developed instrumentation and processing base, a new PV-cell concept demands the surface treatments of both sides of the wafers to be decoupled [10].
It appears that it is much more difficult to achieve the high level of surface passivation required for lowering the density of interface defects if the backside surface is rough. A rougher surface has a much larger effective area and therefore more sites where harmful defects can be present. New cell concepts feature a very good surface passivation with a dielectric layer on the backside and local contacts to the silicon. Therefore, in solar cell structures, a non-textured backside surface is needed to reach low effective recombination velocities, enhanced light trapping, and high PCE.
Plasma processes
As opposed to the wet texturing methods, plasma processes have the attribute of less dangerous handling, easier waste disposal, reduced use of DI water and singlesided etching that permits new backside concepts. They offer new possibilities for multicrystalline materials without saw damage, such as EFG, which cannot be processed using common chemical bath texture methods. A distinction has to be made between reactive ion etching (RIE) and other types of plasma texturing. RIE relies on the ion bombardment texturing, which results in a formation of so-called “black silicon” and creates surface and subsurface damage that has to be removed for further cell processing (dopant diffusion). Process chemistry is based on SF6/O2 [11] or Cl2 [12].
This technique has been proven to yield uniform and low reflectances, providing superior response in a long wavelength region, but the defects induced by the ion bombardment can severely degrade IQE (Fig. 3). A possible solution is etching the damaged region away subsequently by damage removal etch (DRE) – wet chemical processing comprised of alkaline and acidic etch followed by modified acid-peroxide cleaning and final HF dip. DRE can partially diminish the results of texturing in terms of reflectivity; however, this is a necessary trade-off in solar cell processing to keep a low surface recombination velocity (SRV.
One of the alternatives to RIE is a process based on microwave-powered antennas [13]. These antennas are positioned above the substrates, providing sufficient radical density to cause chemical etching on the surface. Ions do not play a role in this process unless an RF bias is applied. Process gases are SF6, N2O and Cl2. The process is self-masking in that the residues of the etching process temporarily get deposited on the surface, leading to a locally lower etch rate and the formation of a texture.
Another plasma texturing process for silicon wafers was developed using a remote plasma source chemical downstream etcher, where the plasma is ignited by a microwave source situated above the reaction chamber that allows the ions to be trapped before reaching the sample [14]. In contrast to RIE, there is no acceleration of ions by a bias voltage. Reactions on the silicon surface are carried out by radicals. Gases used are SF6 and O2.
No ensuing wet chemical processing is required. When plasma texturing is applied as a replacement for acidic isotexturing in standard, thick (200μm) screen-printed solar cells, it yields similar or only slightly higher conversion effi ciencies. The real benefi t of plasma texturing is apparent in advanced structures and for very thin wafers. Because plasma texturing is inherently a onesided process, it is straightforward to achieve the surface decoupling discussed above, whereas it is a challenge with wet chemistry.
Plasma texturing is also particularly appropriate for wafers produced without surface damage such as Si ribbons and epitaxial layers on low-cost Si substrates, for which no easy wet chemical texturing process is available. This method has brought a signifi cant advantage to both types of substrates [15, 16]. However, there is an important issue associated with plasma texturing: gas abatement.
While replacing wet texturing by plasma texturing would reduce the amount of wastewater dramatically, the release of greenhouse gasses could offset that environmental advantage completely if not properly tackled [17, 18]. SF6, for instance, has a huge global warming potential (GWP) of 24,000. Just a few percent of the SF6 fl ow getting past the abatement system leads to a poor environmental balance, which is unacceptable for a PV product.
This problem is common to several processes in microelectronics and, increasingly, thin-fi lm PVs (reactor etching). Producers of gas and abatement systems have responded to the challenge and are now developing solutions that can lead to zero release of GWP gas, either by effective recycling of the fl uorinated species, or by offering alternative gas systems with low GWP [19].
Novel methods
Lately, novel electrical discharge machining (EDM) texturing method for roughening mc-Si wafers and EFG ribbons for solar cell application have been getting more and more attention. EDM die-sinker uses a specially designed conductive, soft magnetic brush to texture the work piece. Preliminary experimental results show that the throughput of this method can be >1000mm2/minute with a brush of 100mm in diameter. Solar cells made on textured substrates give reasonable output [20].
Conclusion
Moving forward to next-generation solar cell mass production, it is anticipated that new processes will be introduced that enable fast texturing and deep silicon etching on only one side, as surface decoupling is desired. An emerging fi eld is that of plasma-based Si etching processes for solar cells. Plasma texturing has proved particularly suitable for advanced solar cell structures and new low-cost substrates.
References